整理_3

WLAN: SDIO
Micro SD: SDIO
GPS: FF-UART
DUAL UART: CPLD External Bus
MDOC: PXA270 External Bus
SDRAM: PXA270 External Bus
CPLD: PXA270 External Bus、JTAG

• CPLD is designed for both high performance and low power applications.
  This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability
  is improved.This device consists of sixteen Function Blocks inter-connected
  by a low power Advanced Interconnect Matrix (AIM).